The SP6_Vision board is a highly customizable extension board which can be connected to the APF27_Dev or APF51_Dev board and dedicated to signal processing.
The board is composed of a large Spartan6 Xilinx FPGA (LX45 to LX150) and two independent mobile DDR
memories. Only a single power supply is required.
The communication with the i.MX processor is done through the first FPGA located on the APFxx. Download of the firmware on the SP6_VISION is done in by using parallel bus in order to reduce the programming time.
Sample code and the download tools are provided by armadeus.
- Single input Power supply: 5..13Vdc
- 1.2Vdc - 2.5A max on board regulator (FPGA core)
- 1.8Vdc - 1.2A max on board regulator (i.MX bus et mobile DDR)
- 2.5Vdc - 1.2A max on board regulator (FPGA VCCAUX)
- 3.3Vdc - 2.5A max on board regulator (FPGA GPIO)
- Spartan6, LX45,LX100 or LX150
- 22 differential lines or 44 single ended lines (2.5 or 3.3V)
- 12 single ended 3.3V lines (1 input and 11 outputs, CSI/user IO)
- Up to 16 lines pre routed between the APFxx FPGA and the SP_VISON FPGA
- 16 bits data bus & 12 bits address connected to the APFxx FPGA
- Available version: none, 2*64 Mbytes or 2*128 Mbytes 16bits mobile DDR
- J4: Power DC Jack (2.5mm)
- J5: 1x6 single row 2.54mm pin header (JTAG)
- J1: 2x17 dual row 2.54mm pin header (user connector)
- J2: 2x10 dual row 2.54mm pin header (user connector)
- J3: 2x17 dual row 2.54mm pin header (user connector)
- J19: 2x21 dual row 2.54mm pin header (APFxxDev J19)
- J20: 2x20 dual row 2.54mm pin header (APFxxDev J20)
Recommended processor boards
Mechanical overview - Environment
- Size: 100 mm x 100 mm ( 3.93” x 3.93” )
- Operating temperature: 0°C to +75°C